1. Field of the Invention
The present invention relates generally to a method for manufacturing a capacitor and a method for manufacturing a semiconductor device incorporating the capacitor. More particularly, the present invention relates to a method for manufacturing a capacitor without damaging a storage electrode thereof, and a method for manufacturing a semiconductor device incorporating the capacitor.
A claim of priority is made to Korean Patent Application No. 2003-89397 filed on Dec. 10, 2003, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
As the level of integration in conventional semiconductor memory devices increases, the area taken up by a single memory cell unit in a semiconductor memory device decreases accordingly. To ensure sufficient storage capacitance in the semiconductor memory device, a capacitor generally takes on one of various shapes such as a box, a fin, a crown, or a cylinder. One conventional capacitor comprises a cylindrical storage electrode connected to a contact pad formed on a semiconductor substrate. Such a capacitor having a cylindrical storage electrode is typically formed using a mold layer. A conventional method for forming a capacitor using a mold layer is disclosed, for example, in U.S. Pat. No. 6,482,696, Japanese Laid Open Patent Publication No. 2001-210804, and Korean Laid Open Patent Publication No. 2003-67821.
FIGS. 1A through 1E are cross-sectional views illustrating a method for forming a conventional capacitor using a mold layer.
Referring to FIG. 1A, an insulating interlayer 5 is formed on a semiconductor substrate (not shown) including contact regions. The insulating interlayer 5 is then partially etched by a photolithography process to form openings that expose the contact regions in the semiconductor substrate.
A first conductive layer of polysilicon or metal is formed on the insulating interlayer 5 to fill the openings. The first conductive layer is etched by a chemical mechanical polishing (CMP) process or an etch-back process until the insulating interlayer 5 is exposed, thereby forming contacts 10 filling the openings.
An etch-stop layer 15, a mold layer 20, and a mask layer are successively formed on the insulating interlayer 5 and the contacts 10. A photoresist pattern 30 is then formed on the mask layer.
Using the photoresist pattern 30 as an etching mask, the mask layer is patterned to form a storage electrode mask 25 on the mold layer 20. The mold layer 20 and the etch-stop layer 15 are partially etched using the storage electrode mask 25 such that storage electrode contact holes 35 are formed through the mold layer 20 and the etch-stop layer 15. The storage electrode contact holes 35 expose the contacts 10.
Referring to FIG. 1B, the photoresist pattern 30 is removed by an ashing and/or stripping process and a second conductive layer 40 of doped polysilicon is formed on the contacts 10, on inner sidewalls of the storage electrode contact holes 35 and on the storage electrode mask 25.
Referring to FIG. 1C, a sacrificial oxide layer 50 is formed on the second conductive layer 40, thereby filling the storage electrode contact holes 35.
Referring to FIG. 1D, storage electrodes 60, which are electrically connected to contacts 10, are formed using a CMP process. The CMP process is used to remove portions of the sacrificial oxide layer 50, the second conductive layer 40, and the storage electrode mask 25, until the mold layer 20 is exposed. Each of the storage electrodes 60 has a cylindrical shape with a patterned sacrificial layer 55 filling a gap between sections of the cylindrical storage electrode 60.
Referring to FIG. 1E, the storage electrodes 60 are completed by removing the mold layer 20 and the patterned sacrificial layer 55. Dielectric layers 65 and plate electrodes 70 are then successively formed on the storage electrodes 60 to form capacitors 75 on the semiconductor substrate.
The method described above has at least one significant shortcoming. In forming the capacitors 75 using the mold layer 20, an upper portion of the resulting storage electrodes 60 is removed by the CMP process which is applied to remove the storage electrode mask 25. When this upper portion of the storage electrode 60 is removed, the effective area of the storage electrode 60 is reduced, thus reducing the overall capacitance of the capacitor 75.